Showing 1–12 of 12 results
/ Date/ Name
Mar 23, 2016Efficient Enumeration of Unidirectional Cuts for Technology Mapping of Boolean NetworksApr 17, 2022A Novel ASIC Design Flow using Weight-Tunable Binary Neurons as Standard CellsJun 15, 2023ECO-CHIP: Estimation of Carbon Footprint of Chiplet-based Architectures for Sustainable VLSIApr 13, 2020Enabling Incremental Knowledge Transfer for Object Detection at the EdgeOct 10, 2019Threshold Logic in a FlashNov 30, 2021CIDAN: Computing in DRAM with\\Artificial NeuronsOct 25, 2007Stochastic Power Grid Analysis Considering Process VariationsApr 4, 2021A Configurable BNN ASIC using a Network of Programmable Threshold Logic Standard CellsOct 19, 2019ELSA: A Throughput-Optimized Design of an LSTM Accelerator for Energy-Constrained DevicesMar 7, 2024HeteroSwitch: Characterizing and Taming System-Induced Data Heterogeneity in Federated LearningMar 23, 2016Digital IP Protection Using Threshold Voltage ControlSep 30, 2025A Compact, Low Power Transprecision ALU for Smart Edge Devices