Showing 1–20 of 21 results
/ Date/ Name
Oct 24, 2025QuArch: A Benchmark for Evaluating LLM Reasoning in Computer ArchitectureSep 22, 2025Lightweight Congruence Profiling for Early Design Exploration of Heterogeneous FPGAsJun 3, 2025Fast Machine Learning for Quantum Control of Microwave Qudits on Edge HardwareJan 14, 2022Real-time Inference with 2D Convolutional Neural Networks on Field Programmable Gate Arrays for High-rate Particle Imaging DetectorsAug 13, 2021Scaling Up Hardware Accelerator Verification using A-QED with Functional DecompositionAug 4, 2022Neural network accelerator for quantum controlJan 3, 2021DB4HLS: A Database of High-Level Synthesis Design Space ExplorationsFeb 19, 2019Securing Accelerators with Dynamic Information Flow TrackingJun 4, 2022Enabling Heterogeneous, Multicore SoC Research with RISC-V and ESPJul 2, 2020CRYLOGGER: Detecting Crypto Misuses DynamicallyDec 18, 2019COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware AcceleratorsApr 16, 2020The MosaicSim Simulator (Full Technical Report)Dec 18, 2019PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled AcceleratorsJul 8, 2025SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided DesignNov 20, 2024Machine Learning for Arbitrary Single-Qubit Rotations on an Embedded DeviceJan 12, 2022Accelerating Deep Neural Networks for Real-time Data Selection for High-resolution Imaging Particle DetectorsJul 4, 2024Towards Generalized On-Chip Communication for Programmable Accelerators in Heterogeneous ArchitecturesSep 2, 2020Agile SoC Development with Open ESPMar 9, 2021hls4ml: An Open-Source Codesign Workflow to Empower Scientific Low-Power Machine Learning DevicesSep 14, 2021Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs