Showing 1–16 of 16 results
/ Date/ Name
Dec 7, 2020The Tribes of Machine Learning and the Realm of Computer ArchitectureJul 7, 2020The gem5 Simulator: Version 20.0+Oct 25, 2020Performance Analysis of Scientific Computing Workloads on Trusted Execution EnvironmentsAug 26, 2016When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data WorkloadsMar 23, 2023A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5Mar 23, 2023Enabling Design Space Exploration of DRAM Caches in Emerging Memory SystemsApr 4, 2024TEGRA -- Scaling Up Terascale Graph Processing with Disaggregated ComputingAug 6, 2024Potential and Limitation of High-Frequency Cores and CachesJun 30, 2023FP-Rowhammer: DRAM-Based Device FingerprintingNov 25, 2025Pickle Prefetcher: Programmable and Scalable Last-Level Cache PrefetcherSep 2, 2025Portable Targeted Sampling Framework Using LLVMOct 30, 2025Choreographer: A Full-System Framework for Fine-Grained Tasks in Cache HierarchiesDec 15, 2025Toward Reproducible and Standardized Computer Architecture Simulation with gem5Apr 22, 2024TDRAM: Tag-enhanced DRAM for Efficient CachingMay 8, 2025Characterizing GPU Energy Usage in Exascale-Ready Portable Science ApplicationsMar 6, 2026Space-Control: Process-Level Isolation for Sharing CXL-based Disaggregated Memory