Showing 1–20 of 62 results
/ Date/ Name
Jul 9, 2021NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement LearningSep 7, 2022TAG: Learning Circuit Spatial Embedding From LayoutsDec 19, 2020MAVIREC: ML-Aided Vectored IR-DropEstimation and ClassificationNov 28, 2024DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous AgentAug 20, 2024Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code GenerationAug 23, 2024Intelligent OPC Engineer Assistant for Semiconductor ManufacturingApr 26, 2025Apollo: Automated Routing-Informed Placement for Large-Scale Photonic Integrated CircuitsJul 8, 2022Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self TrainingMar 12, 2022Generic Lithography Modeling with Dual-band Optics-Inspired Neural NetworksDec 15, 2024ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic InterpolationApr 28, 2025Deep Generative Prior for First Order Inverse OptimizationFeb 22, 2026Pushing the Limits of Inverse Lithography with Generative Reinforcement LearningApr 16, 2026Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABCSep 14, 2023VerilogEval: Evaluating Large Language Models for Verilog Code GenerationNov 26, 2020FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter TuningSep 19, 2024CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code RepairSep 20, 2024Learning to Compare Hardware Designs for High-Level SynthesisFeb 8, 2024Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient DescentNov 28, 2023RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language ModelsMar 28, 2025Learning Library Cell Representations in Vector Space