Showing 1–17 of 17 results
/ Date/ Name
Jan 29, 2025When Everyday Devices Become Weapons: A Closer Look at the Pager and Walkie-talkie AttacksOct 9, 2023LLM for SoC Security: A Paradigm ShiftMay 11, 2025ThreatLens: LLM-guided Threat Modeling and Test Plan Generation for Hardware Security VerificationOct 6, 2025DeepV: A Model-Agnostic Retrieval-Augmented Framework for Verilog Code Generation with a High-Quality Knowledge BaseApr 16, 2026Emulation-based System-on-Chip Security Verification: Challenges and OpportunitiesApr 2, 2026Assertain: Automated Security Assertion Generation Using Large Language ModelsApr 2, 2026AI-Assisted Hardware Security Verification: A Survey and AI Accelerator Case StudyJun 25, 2025SV-LLM: An Agentic Approach for SoC Security Verification using Large Language ModelsMay 28, 2025BugWhisperer: Fine-Tuning LLMs for SoC Hardware Vulnerability DetectionApr 17, 2022Quantifiable Assurance: From IPs to PlatformsJul 22, 2025SVAgent: AI Agent for Hardware Security Verification AssertionMay 7, 2026CircuitFormer: A Circuit Language Model for Analog Topology Design from Natural Language PromptMay 22, 2022Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and ApplicationsJul 20, 2019Defense-in-Depth: A Recipe for Logic Locking to PrevailJan 6, 2026LAsset: An LLM-assisted Security Asset Identification Framework for System-on-Chip (SoC) VerificationJul 9, 2025VerilogDB: The Largest, Highest-Quality Dataset with a Preprocessing Framework for LLM-based RTL GenerationMay 7, 2026ChartZero: Synthetic Priors Enable Zero Shot Chart Data Extraction