Showing 1–20 of 21 results
/ Date/ Name
Sep 28, 2024RTL2M$μ$PATH: Multi-$μ$PATH Synthesis with Applications to Hardware Security VerificationJan 3, 2026CounterPoint: Using Hardware Event Counters to Refute and Refine Microarchitectural Assumptions (Extended Version)Dec 20, 2021Relational Models of Microarchitectures for Formal Security AnalysesAug 26, 2016TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISAAug 8, 2020TransForm: Formally Specifying Transistency Models and Synthesizing Enhanced Litmus TestsFeb 11, 2018MeltdownPrime and SpectrePrime: Automatically-Synthesized Attacks Exploiting Invalidation-Based Coherence ProtocolsNov 4, 2016Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler MappingsSep 11, 2023Serberus: Protecting Cryptographic Code from Spectres at Compile-TimeApr 22, 2025VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness ValidationFeb 3, 2026LLM-FSM: Scaling Large Language Models for Finite-State Reasoning in RTL Code GenerationMay 9, 2021Analysis and Mitigations of Reverse Engineering Attacks on Local Feature DescriptorsAug 13, 2021Scaling Up Hardware Accelerator Verification using A-QED with Functional DecompositionMay 2, 2021SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure ComputingJan 19, 2021Porcupine: A Synthesizing Compiler for Vectorized Homomorphic EncryptionMar 8, 2023nl2spec: Interactively Translating Unstructured Natural Language to Temporal Logics with Large Language ModelsAug 5, 2025Towards Memory Specialization: A Case for Long-Term and Short-Term RAMJan 25, 2022RecShard: Statistical Feature-Based Memory Optimization for Industry-Scale Neural RecommendationApr 18, 2022Dynamic Network Adaptation at InferenceNov 5, 2020CPR: Understanding and Improving Failure Tolerant Training for Deep Learning Recommendation with Partial RecoveryJan 29, 2021RecSSD: Near Data Processing for Solid State Drive Based Recommendation Inference