Monolithic CMOS pixel R&D for the ILC at LBNL

The anticipated ILC physics program requires pixel sensors with performances well beyond those obtained for the experiments at LHC in terms of single point resolution and material budget. At the same time the ILC experimental environment, with its lower event rate and radiation flux, admits Si sensors that are substantially thinner, more precise and more segmented than at the LHC and thus motivates new directions for R&D to achieve these performance [1]. LBNL has played a major role in Si detector development and it is currently engaged in a number of related projects, including the ATLAS pixel project, thick CCD development for SNAP, CMOS pixel R&D for the STAR upgrade and also CPCCDs and CMOS pixels for application at synchrotron light sources and electron microscopy. Monolithic CMOS pixel sensors offer several desirable features for application in collider experiments. The STAR experiment at RHIC has engaged in the first vertex detector based on CMOS pixels, under the guidance of the STAR group at LBNL. The ILC R&D program aims at addressing key R&D issues, building on the significant know how established at LBNL, and exploiting synergies and opportunities at the interface between these different fields of applications. The R&D program on CMOS pixel sensors for the ILC started in Fall 2004 and it is addressing three main issues: the characterization of pixel sensors and the simulation of their response in the ILC physics and background environment, the test and characterization of thinned pixel sensors and the design and testing of new pixel test structures embedding on chip data reduction capabilities to specifications set by the ILC requirements. This paper reviews the project activities after the first semester of the R&D program.