AGON: Automated Design Framework for Customizing Processors From ISA Documents

Customized processors are essential for domain-specific applications such as the Internet of Things (IoT) and multimedia embedded systems, yet their design often requires extensive expert intervention. Traditional approaches, including hardware design using encapsulated abstractions (e.g., Chisel) and high-level synthesis (HLS) from languages like C or SystemC, reduce some manual efforts but remain either costly or suboptimal. Recent explorations into leveraging large language models (LLMs) to generate register-transfer level (RTL) from natural language specifications have shown promise, but these methods still struggle with generating complex and high-performance processors, mainly due to the complicated low-level details in the RTL code. In this work, we introduce AGON, a novel framework designed to facilitate the development of customized processor RTL from instruction set architecture (ISA) documents using LLMs. The framework comprises two layers: a functional description layer and a hardware implementation layer. At the functional layer, AGON employs a nano-operator (nOP)-based intermediate representation (IR) that abstracts basic instruction operations, thereby reducing the semantic gap between natural language and the RTL code. This abstraction significantly shortens the descriptive code required for LLM generation, improving the generation accuracy in a single pass. At the hardware layer, AGON offers three abstraction levels (i.e., instruction, ISA, and processor) along with rule-based primitives to systematically lower the nOP-based IR into a fully optimized processor implementation. This decoupled design not only ensures correctness-by-construction but also enables automated, power, performance, and area (PPA)-aware performance optimization. We evaluate AGON by designing high-performance out-of-order (OoO) processors that correctly execute practical programs. Experimental results demonstrate that processors generated with AGON achieve an average speed of $4.51\times $ on specific tasks compared to expert-designed general-purpose central processing units (CPUs) while requiring minimal design effort.