PALS: Distributed Gradient Clocking on Chip

Consider an arbitrary network of communicating modules on a chip, each requiring a local signal telling it when to execute a computational step. There are three common solutions to generating such a local clock signal: 1) by deriving it from a single, central clock source; 2) by local, free-running oscillators; or 3) by handshaking between neighboring modules. Conceptually, each of these solutions is the result of a perceived dichotomy in which (sub)systems are either clocked or asynchronous. We present a solution and its implementation that lies between these extremes. Based on a distributed gradient clock synchronization (GCS) algorithm, we show a novel design providing modules with local clocks, the frequency bounds of which are almost as good as those of free-running oscillators, yet neighboring modules are guaranteed to have a phase offset substantially smaller than one clock cycle. Concretely, parameters obtained from a 15-nm application specific integrated circuit (ASIC) simulation running at 2 GHz yield mathematical worst-case bounds of 20 ps on the phase offset for a $32\,\, \times 32$ node grid network.