Development of CMOS pixel sensors for tracking and vertexing in high energy physics experiments

CMOS pixel sensors (CPS) represent an emerging technological approach to charged particle detectors. CMOS processes allow to integrate the sensitive volume and the readout elec- tronics of the pixel detector in a single silicon die allowin g for small pixel pitch (. 20 μm) and low material budget (∼ 0.2-0.3% X0 per layer). These characteristics make CPS an attractive op- tion for vertexing and tracking systems of high energy physics experiments requiring high spatial resolution. Moreover, thanks to the use of commercial CMOS processes for the CPS fabrication, the construction cost can be significantly reduced in compar ison to the custom technologies used so far. However, the attainable performance level of the CPS in terms of radiation hardness and readout speed is mostly determined by the fabrication parameters of the CMOS processes available on the market rather than by the CPS intrinsic potential itself. The constant evolution of commercial CMOS processes towards smaller feature sizes and high re- sistivity epitaxial layers enhances steadily the radiatio n hardness and allows for the implementation of more complex, accelerated readout circuits. The TowerJazz 0.18 μm CMOS process, being one of the most relevant examples, recently became of interest for several future detector projects. The most imminent of them is an upgrade of the Inner Tracking System (ITS) of the ALICE detec- tor at LHC. It will be followed by the Micro-Vertex Detector (MVD) of the CBM experiment at FAIR. Other experiments like ILD consider CPS as one of the viable options for flavour tagging and tracking sub-systems. Following the successful tests of the first prototypes in 201 2 proving that the radiation hardness of the technology complies with the requirements of the new ALICE-ITS and CBM-MVD, the PICSEL group of IPHC-CNRS in Strasbourg (France) started to develop two CPS (MISTRAL and ASTRAL) dedicated to these projects. The present contribution describes the current status of this development. Results of the laboratory and beam tests of several prototype chips manufactured in Spring and tested during Summer 2013 are presented.